1. Field of the Invention
Example embodiments of the present disclosure relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having a trench isolation layer and methods of fabricating the same.
2. Description of the Related Art
As semiconductor devices become more integrated, design rules of circuit patterns have been reduced. Accordingly, isolation layers of semiconductor devices continuously shrink. That is, the isolation layers having ultra-fine sizes are increasingly demanded to realize highly integrated semiconductor devices. However, when design rules of semiconductor devices such as dynamic random access memory (DRAM) devices are reduced to about 30 nanometers or less, voids and/or seams may be formed in shallow trench isolation (STI) layers of the semiconductor devices. Thus, isolation techniques for forming the isolation layers without any voids and/or seams have been increasingly demanded to fabricate high reliable semiconductor devices.
Recently, methods of forming isolation layers with a spin on dielectric (SOD) layer or a flowable oxide layer have been proposed to obtain excellent isolation layers without voids and/or seams. However, the SOD layer may contain impurities such as carbon hydride (CH) and the flowable oxide layer may contain impurities such as nitrogen hydride (NH). Thus, during removal of the nitride hydride (NH) or the carbon hydride (CH), the SOD layer or the flowable oxide layer may shrink and/or increase in density. That is, a volume of the SOD layer or the flowable oxide layer may be reduced after removal of the impurities therein. The reduction of the volume of the SOD layer or the flowable oxide layer may cause a stress, thereby generating crystalline defects in a substrate (or a wafer) adjacent to the SOD layer or the flowable oxide layer. Further, if the stress of the SOD layer or the flowable oxide layer increases, the wafer may warp.